Neural network architectures for associative memory

The work reported is concerned with goals which belong to hardware implementations of neural networks as a parallel architecture for the solution of engineering problems. In the context, artificial neural networks represent a new computational style with the inherent advantages of fine-grain parallelism, speed and fault-tolerance. We have been developing programmable VLSI neural network devices using hybrid analogue/digital CMOS technology. The pulse-stream signalling mechanism which we have developed is analogous to that found in natural neural systems in that pulses are used to transmit information: this leads to an efficient implementation of the analogue synaptic multiply-and-add function requiring less than 5 transistors per synapse. With our current design, it is possible to fabricate single-chip VLSI devices with as many as 10,000 synaptic weighting operators.